L.A.A.R. - Vol.37 - 2007

Special Issue on Programmable Logic II Southern Conference on Programmable Logic (SPL2006) - Mar del Plata, Argentina, March 8-10, 2006. CONTENTS
G. Sutter, H. A Larrondo, J. L. Figueroa	PREFACE	1
INVITED PAPER
J.-P. Deschamps	CRYPTOGRAPHIC APPLICATIONS IN FPGA	3
SPECIAL ISSUE PAPERS
L. Agostini, R. Porto, M. Porto, T. Silva, L. Rosa, J. Güntzel, I. Silva, S. Bampi	FORWARD AND INVERSE 2-D DCT ARCHITECTURES TARGETING HDTV FOR H.264/AVC VIDEO COMPRESSION STANDARD	11
L. Arnone, C. Gayoso, C. González, J. Castiñeira	SUM-SUBTRACT FIXED POINT LDPC DECODER	17
G. Calin, V. O. Roda	REAL-TIME DISPARITY MAP EXTRACTION IN A DUAL HEAD STEREO VISION SYSTEM	21
M. J. Moure, P. Rodiz, M. D. Valdés, L. Rodriguez-Pardo, J. Fariña	AN FPGA-BASED SYSTEM FOR THE MEASUREMENT OF FREQUENCY NOISE AND RESOLUTION OF QCM SENSORS	25
M. C. Sacchetin, J. J. Lopes, D. F. Wolf, J. L. Silva, E. Marques	ANALYSIS AND IMPLEMENTATION OF LOCALIZATION AND MAPPING ALGORITHMS FOR MOBILE ROBOTS BASED ON RECONFIGURABLE COMPUTING	31
R. Cayssials, M. Duval, E. Ferro, O. Alimenti	uRT51: AN EMBEDDED REAL-TIME PROCESSOR IMPLEMENTED ON FPGA DEVICES	35
A. Chacón-Rodríguez, F. N. Martín-Pirchio, P. Julián, P. S. Mandolesi	A VERILOG HDL DIGITAL ARCHITECTURE FOR DELAY CALCULATION	41
R. García-Retegui, S. A. González, M. Funes	FLEXIBLE FPGA INTERFACE FOR THREE-PHASE POWER MODULES	47
J. Castillo, P. Huerta, J. I. Martínez	AN OPEN-SOURCE TOOL FOR SYSTEMC TO VERILOG AUTOMATIC TRANSLATION	53
M. de Alba, A. Andrade, J. González, J. Gómez-Tagle, A. D. García	FPGA DESIGN OF AN EFFICIENT AND LOW-COST SMART PHONE INTERRUPT CONTROLLER	59
A. Molina, O. Cadenas	FUNCTIONAL VERIFICATION: APPROACHES AND CHALLENGES	65
M. C. Liberatori, J. C. Bonadero	AES-128 CIPHER. MINIMUM AREA, LOW COST FPGA IMPLEMENTATION	71
C. González-Concejero, V. Rodellar, A. Álvarez-Marquina, E. Martínez de Icaya, P. Gomez-Vilda	A PORTABLE HARDWARE DESIGN OF A FFT ALGORITHM	79
D. R. Llamocca-Obregón, C. P. Agurto-Ríos	A FIXED-POINT IMPLEMENTATION OF THE EXPANDED HYPERBOLIC CORDIC ALGORITHM	83
J-P. Deschamps, G. Sutter	COMPARISON OF FPGA IMPLEMENTATION OF THE MOD M REDUCTION	93
G. Sutter, E. Boemo	EXPERIMENTS IN LOW POWER FPGA DESIGN	99