POWER CONSUMPTION OPTIMIZATION IN REED SOLOMON ENCODERS OVER FPGA
This paper presents an analysis of the Reed Solomon encoder model and GF (2m) multiplier component, with the aim of optimizing the power consumption for reconfigurable hardware. The methods used consisted of concatenation and reassignment circuit signals in the VHDL description. This treatment allowed achieving a reduction in the consumption of hardware resources and optimizing power consumption in the multiplier of 7.89%, which results in a reduction of the dynamic power of a 42.42% in the coder design optimized. With this development, it provides a design method with good performance, which can be applied to other circuits.
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